`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/29 20:56:05
// Design Name: 
// Module Name: float_mul
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module float_mul(
    input wire clk,
    input wire a_tvalid,
    input wire [31:0] a_tdata,
    input wire b_tvalid,
    input wire [31:0] b_tdata,
    input wire mul_result_tready,
    output wire mul_result_tvalid,
    output wire [31:0] mul_result_tdata
    );
    
    float_multiply u1_float_multiply(                       //乘法器
    .aclk(clk),
    .s_axis_a_tvalid(a_tvalid),
    .s_axis_a_tdata(a_tdata),
    .s_axis_b_tvalid(b_tvalid),
    .s_axis_b_tdata(b_tdata),
    .m_axis_result_tvalid(mul_result_tvalid),
    .m_axis_result_tready(mul_result_tready),
    .m_axis_result_tdata(mul_result_tdata)
);

endmodule
